Computer processors use a primary storage facility to store the results of processed instructions and to pass data from one instruction to another. The primary storage reduces execution time of a program by providing immediate storage for the data being processed thus avoiding any delay in transferring the data to and from memory. In the Itanium™ architecture, for example, the primary storage is referred to as a Register Stack and in the Sun SPARC™ architecture the primary storage is referred to as a Register Window.
Generally, register stacks are finite in size and as a result, as call depth increases during the execution of a set of instructions the processor needs to save the data in some of the registers in a secondary storage facility or memory. Saving register contents to memory frees up registers for the processing of subsequent sets of instructions or procedure/function calls. The SPARC™ architecture generates a trigger in the software called a trap to initiate the saving of registers to create free registers. This method works well when the call depths are shallow or when the program depth does not change significantly to cause register window overflow. Traps are however computationally expensive as outlined in 64-bit CPUs: Alpha, SPARC, MIPS and Power, by Jim Turley, Feb. 21, 2002. The Itanium™ architecture avoids the use of traps by employing a Register Save Engine (RSE) which automatically saves registers to memory. The RSE can operate in two alternative modes. In the first mode is called the lazy mode and in this mode only a new stack frame allocation triggers the RSE to save registers to memory. The second mode is called the eager and in this mode registers are saved as and when the memory bus is idle. The register saves/restores in eager mode can occur any time, not necessarily during the procedure entry and exit.
The modes of operation of the Itanium™ RSE each have drawbacks in different scenarios. Given a register stack with more free registers than are required to complete the execution of the procedure sequence, the processor would not be required to perform any register stack saves (or restores). However, if the RSE mode of operation is set to eager, the processor will aggressively pursue saving and loading back registers across the procedure call/returns, resulting unnecessary memory traffic. If the RSE operation was set to lazy mode, and program execution requires more registers then are free, the operation of the RSE may stall the execution of the program whenever a procedure's register requirement exceeds the available clean registers in the register stack.
It is an object of the present invention to provide a method and apparatus for managing storage used by a processor when processing instructions, which avoids some of the above disadvantages or at least provides a useful alternative.